“A” series, 5μm BJT processes, are categorized by transistor breakdown voltage (BVCEO). Besides its basic BJT functions, Episil also offers customers several option layers, (e.g., implant resistor, capacitor and deep p+) for special requirements.

“C” series, 1.5μm BJT processes, are developed to minimize the device size by utilizing 1.5μm design rule and double buried layers. The cutoff frequency of NPN transistor made by this process can reach 2.5GHz, and an ultra flat zone of Hfe for Ic=1nA to 1mA is also achieved. Three processes are widely used in power management (Linear and Switching Mode), motor control, optical sensor, low dropout (LDO) and Hall sensor, etc.

Embedded NVM process
Episil supports its process technologies with highly competitive embedded memory cells, including 0.5μm Flat-cell ROM, 0.7μm EEPROM,1 .2μm EEPROM and 0.5μm OTP. With the cells, the design company can design its embedded NVM application products to specific density and configuration into 0.7μm, 1.2μm EEPROM, 0.5μm Flat-cell ROM and 0.5μm OTP process technology. Embedded NVM process is currently available in 0.7μm EEPROM, 1.2μm EEPROM, 0.5μm Flat-cell and OTP process. High performance and low power consumption are implemented in the embedded NVM design for many consumer ICs, micro-control application products.

HV CMOS process and Mix-Mode process
Episil offers comprehensive high voltage technologies suitable for high-voltage and power integrated circuits with the 0.8um HV CMOS process. The applications are for display driver products, power management, automotive electronics and industrial controls. The spice model and design rule documents are currently available for customers’ design needs, and Episil also provides 0.8um 5V/12V, 5V/18V,and 5V/30V technology for different applications. An oxide capacitor and poly resistor are options for High-Voltage Mix-Mode products and applications.

Logic CMOS and Mix-Mode process
Episil offers comprehensive CMOS Logic process for customers to design logic application products. The process technology is based from 2.0 μm to 0.5μm. The logic CMOS process, above 0.6μm (0.8μm/5V, 1.0μm/9V, 1.2μm, 1.5μm and 2.0μm technology), running in 5”line, is based on the single poly and double metal layers structure which allow customers’ design legacy or Pad limited products. A 0.5μm logic process is based on the single poly or double poly (for mix-mode) and double metal /triple metal layers structure running in Episil 6” line. It is suitable for customers to design 0.5 μm logic/mix-mode or for embedding Flat-cell ROM products. The technology documents for these processes are available for customers.

Low Voltage Logic process
For many portable, low power consumption application products, Episil offers 0.5 μm low voltage process. The layout design rule is the same as 0.5μm/5V application process; the device threshold voltage is lower than the typical 5V CMOS technology. The technology documents are available for customers’application.

Power Device Process
Episil offers Power Device Process, including IGBT, Discrete, Power-MOSFET, Trench Power-MOSFET, etc., foundry services with up to 0.6μm VDMOS Process and HV-Series VDMOS Process.

The 0.6μm VDMOS process is either a vertical planar or Trench structure, based on a single poly and metal structure. There are completed backend processes available, including back grinding, back metal evaporation, and optional probing/testing service.  Based on the functional demands from customers, functional value-added devices are available to be merged into Episil’s 0.6μm VDMOS, such as poly-diode, poly-fuse and JFET. 

HV-series VDMOS processes range from 200V to 850V blocking voltage. Guard ring and field plate structure are used in these HV-series VDMOS processes to sustain high blocking voltage.
These processes have been widely used in the system of power management, motor control, optical sensor, such as pulse width modulator PWM and anything that needs switching or driving capability.